Microcomputers are also referred to as microprocessors. As the throughput capacity is enhanced, microprocessors of multi-core configuration (referred to as “multi-core processor”) high in processing performance per power consumption have received attention in the field of embedded devices as well.
Microprocessors of multi-core configuration are classified into those of symmetric multi processor (SMP: Symmetric Multi Processor) configuration and asymmetric multi processor (AMP: Asymmetric Multi Processor) configuration. The symmetric multi processor (SMP) is so constructed that the multiple CPUs incorporated in the processor completely evenly operate and the same operation and processing can be carried out in every CPU. That is, the symmetric multi processor is a system in which there is no CPU to which master operation is solely assigned and all the CPUs take partial charge of operating system (OP) functions and the like. In the symmetric multi processor SMP, processes are divided by dividing a task into threads and can be distributedly carried out by any processor. Therefore, the symmetric multi processor lacks certainty with respect to task execution time and sequence and real-time performance.
A system including a symmetric multi processor is capable of simultaneously executing threads in proportion to the number of CPUs by assigning the individual threads to the CPUs and this makes it possible to enhance the processing performance of the entire system. In asymmetric multi processors (AMPs), meanwhile, the use of each CPU is predetermined and each CPU is not used for uses other than the predetermined use.
One of examples of documents in which a parallel distributed processing system is described is Patent Document 1. In the parallel distributed processing system in Patent Document 1, the address spaces of each processor are divided into spaces shared among multiple threads and spaces such as stacks not shared among threads. Each processor is provided with a CPU address-logical address translation circuit. When the latter space, or the non-shared space, is accessed, the value of a base register is added to the access request address and address translation is carried out. The address spaces such as stacks are thereby relativized so that parallel translation can be arbitrarily carried out.
[Patent Document 1] Japanese Unexamined Patent Publication No. Hei 9(1997)-146904